1. Field of the Invention
The present invention relates in general to a CMOS input circuit, and more particularly to an input circuit for changing a potential into a different potential of the same logic level.
2. Description of the Background Art
FIG. 23 is a circuit diagram of a conventional CMOS input circuit 70. The CMOS input circuit 70 comprises a P-channel transistor 71 and an N-channel transistor 72. The P-channel transistor 71 and the N-channel transistor 72 are provided with potentials V.sub.CC and V.sub.EE, respectively, corresponding to each level of the binary logic. In response to the logic level of a signal received by an input terminal IN, either of the potentials V.sub.CC or V.sub.EE is applied to an output terminal OUT in a stable state.
A signal from a device of gate array configuration, for example, takes a potential 0 V or 5 V depending on whether the logic level thereof is "L" or "H". In receiving the signal, the potentials V.sub.CC and V.sub.EE for the CMOS input circuit 70 are also 0 V and 5 V, respectively, and accordingly, the output terminal OUT is provided with a potential ranging from 0 V to 5 V.
There is a case, however, where an input circuit which receives a signal from a device taking potentials of 0 V and 5 V corresponding to the logic levels "L" and "H" may be connected through its output terminal to a subsequent stage circuit for processing a signal of potential not ranging from 0 V to 5 V. For example, the subsequent stage circuit takes potentials of -5 V and 5 V corresponding to the logic levels "L" and "H". In this case, the CMOS input circuit 70 has a disadvantage that its output terminal OUT can not be connected directly to the subsequent stage circuit.